74HC165-Q100; 74HCT165-Q100
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
tsu
set-up time
DS to CP, CE; see Figure 10
VCC = 2.0 V
80
16
14
11
4
-
-
-
100
-
-
-
120
-
-
-
ns
ns
ns
VCC = 4.5 V
20
17
24
20
VCC = 6.0 V
3
CE to CP and CP to CE;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
5
17
20
Dn to PL; see Figure 11
VCC = 2.0 V
80
16
14
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
17
20
th
hold time
DS to CP, CE and Dn to PL;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
5
5
5
6
2
2
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 6.0 V
CE to CP and CP to CE;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
5
5
5
17
6
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 6.0 V
5
fmax
maximum
frequency
CP input; see Figure 7
VCC = 2.0 V
6
17
51
61
56
35
-
-
-
-
-
5
-
-
-
-
-
4
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
30
35
-
24
28
-
20
24
-
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
[3]
CPD
power
per package;
-
-
-
dissipation
capacitance
VI = GND to VCC
74HC_HCT165_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 17 July 2012
9 of 21
NXP [ NXP ]
