74HC164; 74HCT164
Philips Semiconductors
8-bit serial-in, parallel-out shift register
V
I
V
M
MR input
GND
t
t
rem
W
V
I
CP input
V
M
GND
t
PHL
V
OH
V
Qn output
M
V
OL
001aac427
(1) 74HC164: VM = 50 %; VI = GND to VCC
.
74HCT164: VM = 1.3 V; VI = GND to 3 V.
Fig 8. Waveforms showing the master reset (MR) pulse width, the master reset to output
(Qn) propagation delays and the master reset to clock (CP) removal time
V
I
V
CP input
M
GND
t
t
su
su
t
t
h
h
V
I
V
Dn input
M
GND
V
OH
V
Qn output
M
V
OL
001aac428
(1) 74HC164: VM = 50 %; VI = GND to VCC
.
74HCT164: VM = 1.3 V; VI = GND to 3 V.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
Fig 9. Waveforms showing the data set-up and hold times for Dn inputs
9397 750 14693
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 4 April 2005
15 of 24
NXP [ NXP ]
