74HC164; 74HCT164
Philips Semiconductors
8-bit serial-in, parallel-out shift register
Table 10: Dynamic characteristics for 74HCT164 …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
Max
Unit
tW
clock pulse width;
HIGH or LOW
VCC = 4.5 V;
see Figure 7
27
-
-
ns
master reset pulse width; VCC = 4.5 V;
27
24
18
4
-
-
-
-
-
-
-
-
-
-
ns
LOW
see Figure 8
trem
tsu
removal time MR to CP
VCC = 4.5 V;
see Figure 8
ns
set-up time
DSA and DSB to CP
VCC = 4.5 V;
see Figure 9
ns
th
hold time DSA and DSB VCC = 4.5 V;
ns
to CP
see Figure 9
fmax
maximum clock pulse
frequency
VCC = 4.5 V;
see Figure 7
18
MHz
1/f
max
V
I
CP input
V
t
M
GND
t
W
t
PHL
PLH
V
OH
V
Qn output
M
001aac426
V
OL
(1) 74HC164: VM = 50 %; VI = GND to VCC
.
74HCT164: VM = 1.3 V; VI = GND to 3 V.
Fig 7. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock
pulse width, the output transition times and the maximum clock frequency
9397 750 14693
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 4 April 2005
14 of 24
NXP [ NXP ]
