74HC164; 74HCT164
Philips Semiconductors
8-bit serial-in, parallel-out shift register
Table 9:
Dynamic characteristics for 74HC164 …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
tPHL, tPLH propagation delay
CP to Qn
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
255
51
ns
ns
ns
43
tPHL
propagation delay
MR to Qn
-
-
-
-
-
-
210
42
ns
ns
ns
36
tTHL, tTLH output transition time
-
-
-
-
-
-
110
22
ns
ns
ns
19
tW
clock pulse width;
HIGH or LOW
120
24
-
-
-
-
-
-
ns
ns
ns
20
master reset pulse width; see Figure 7
LOW
VCC = 2.0 V
90
18
15
-
-
-
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
trem
removal time MR to CP
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
90
18
15
-
-
-
-
-
-
ns
ns
ns
tsu
set-up time
DSA and DSB to CP
90
18
15
-
-
-
-
-
-
ns
ns
ns
th
hold time DSA and DSB see Figure 9
to CP
VCC = 2.0 V
4
4
4
-
-
-
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
fmax
maximum clock pulse
frequency
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
4
-
-
-
-
-
-
MHz
MHz
MHz
20
24
9397 750 14693
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 4 April 2005
12 of 24