74HC164; 74HCT164
Philips Semiconductors
8-bit serial-in, parallel-out shift register
Table 10: Dynamic characteristics for 74HCT164
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
tPHL, tPLH propagation delay
CP to Qn
VCC = 4.5 V;
see Figure 7
-
17
19
7
36
38
15
-
ns
tPHL
propagation delay
MR to Qn
VCC = 4.5 V;
see Figure 8
-
ns
tTHL, tTLH output transition time
VCC = 4.5 V;
see Figure 7
-
ns
tW
clock pulse width;
HIGH or LOW
VCC = 4.5 V;
see Figure 7
18
18
16
12
+4
27
7
ns
master reset pulse width; VCC = 4.5 V;
LOW
10
7
-
ns
see Figure 8
trem
tsu
removal time MR to CP
VCC = 4.5 V;
see Figure 8
-
ns
set-up time
VCC = 4.5 V;
see Figure 9
6
-
ns
DSA, and DSB to CP
th
hold time DSA, and DSB VCC = 4.5 V;
−2
55
-
ns
to CP
see Figure 9
fmax
maximum clock pulse
frequency
VCC = 4.5 V;
see Figure 7
-
MHz
Tamb = −40 °C to +85 °C
tPHL, tPLH propagation delay
CP to Qn
VCC = 4.5 V;
see Figure 7
-
-
-
-
-
-
-
-
-
-
45
48
19
-
ns
tPHL
propagation delay
MR to Qn
VCC = 4.5 V;
see Figure 8
-
ns
tTHL, tTLH output transition time
VCC = 4.5 V;
see Figure 7
-
ns
tW
clock pulse width;
HIGH or LOW
VCC = 4.5 V;
see Figure 7
23
23
20
15
4
ns
master reset pulse width; VCC = 4.5 V;
LOW
-
ns
see Figure 8
trem
tsu
removal time MR to CP
VCC = 4.5 V;
see Figure 8
-
ns
set-up time
VCC = 4.5 V;
see Figure 9
-
ns
DSA, and DSB to CP
th
hold time DSA, and DSB VCC = 4.5 V;
-
ns
to CP
see Figure 9
fmax
maximum clock pulse
frequency
VCC = 4.5 V;
see Figure 7
22
-
MHz
Tamb = −40 °C to +125 °C
tPHL, tPLH propagation delay
CP to Qn
VCC = 4.5 V;
see Figure 7
-
-
-
-
-
-
54
57
22
ns
ns
ns
tPHL
propagation delay
MR to Qn
VCC = 4.5 V;
see Figure 8
tTHL, tTLH output transition time
VCC = 4.5 V;
see Figure 7
9397 750 14693
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 4 April 2005
13 of 24
NXP [ NXP ]
