74HC00-Q100; 74HCT00-Q100
NXP Semiconductors
Quad 2-input NAND gate
5. Pinning information
5.1 Pinning
74HC00-Q100
74HCT00-Q100
74HC00-Q100
74HCT00-Q100
terminal 1
index area
2
3
4
5
6
13
12
11
10
9
1B
1Y
2A
2B
2Y
4B
4A
4Y
3B
3A
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
4B
4A
4Y
3B
3A
3Y
1Y
2A
(1)
GND
2B
2Y
8
GND
aaa-003148
Transparent top view
aaa-003147
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
Pin description
Pin
Description
data input
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
data input
data output
ground (0 V)
supply voltage
VCC
14
6. Functional description
Table 3.
Function table[1]
Input
nA
L
Output
nB
X
nY
H
X
L
H
H
H
L
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
74HC_HCT00_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 12 July 2012
3 of 15
NXP [ NXP ]
