74HC00-Q100; 74HCT00-Q100
NXP Semiconductors
Quad 2-input NAND gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC00D-Q100
74HCT00D-Q100
40 C to +125 C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HC00PW-Q100 40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HCT00PW-Q100
74HC00BQ-Q100
74HCT00BQ-Q100
40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
4. Functional diagram
1
3
&
&
&
1
2
1A
1B
2
1Y
2Y
3Y
3
6
8
4
5
4
5
2A
2B
6
9
9
3A
8
10 3B
10
A
B
12 4A
13 4B
12
13
4Y 11
Y
11
&
mna211
mna212
mna246
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
74HC_HCT00_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 12 July 2012
2 of 15
NXP [ NXP ]
