PE3336
Product Specification
Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
Control Interface and Latches (see Figures 3, 4, 5)
fClk
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
10
MHz
ns
tClkH
tClkL
tDSU
30
30
10
ns
Sdata set-up time after Sclk rising edge, D[7:0] set-up time
to M1_WR, M2_WR, A_WR, E_WR rising edge
ns
tDHLD
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
10
ns
tPW
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
30
30
ns
ns
tCWR
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
tCE
Sclk falling edge to E_WR transition
30
30
ns
ns
tWRC
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
tEC
E_WR transition to Sclk rising edge
30
ns
ns
tMDO
MSEL data out delay after Fin rising edge
CL = 12 pf
8
Main Divider (Including Prescaler)
Fin
Operating frequency
Input level range
500
-5
3000
5
MHz
dBm
PFin
External AC coupling
External AC coupling
Main Divider (Prescaler Bypassed)
Fin
Operating frequency
Input level range
50
-5
300
5
MHz
dBm
PFin
Reference Divider
fr
Operating frequency
Reference input power
Input sensitivity
(Note 1)
(Note 2)
-2
100
10
MHz
dBm
VP-P
Pfr
Vfr
Single ended input
External AC coupling
(Note 3)
0.5
Phase Detector
fc
Comparison frequency
(Note 1)
20
MHz
Note 1: Parameter is guaranteed through characterization only and is not tested.
Note 2: Running at low frequencies (< 10 MHz sinewave), the device will still be functional but may cause phase noise degradation. Inserting a low-
noise amplifier to square up the edges is recommended at lower input frequencies.
Note 3: CMOS logic levels may be used if DC coupled. For optimum phase noise performance, the reference input falling edge rate should be faster
than 80mV/ns.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0033-02 │ UltraCMOS™ RFIC Solutions
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