PE3336
Product Specification
input is “low”, serial input data (Sdata input), B0 to
B7, are clocked serially into the enhancement
register on the rising edge of Sclk, MSB (B0) first.
The enhancement register is double buffered to
prevent inadvertent control changes during serial
loading, with buffer capture of the serially entered
data performed on the falling edge of E_WR
according to the timing diagram shown in Figure
5. After the falling edge of E_WR, the data provide
control bits as shown in Table 8 with bit
Direct Interface Mode
Direct Interface Mode is selected by setting the
Bmode input “high”.
Counter control bits are set directly at the pins as
shown in Table 7. In Direct Interface Mode, main
counter inputs M7 and M8, and R Counter inputs
R4 and R5 are internally forced low (“0”).
functionality enabled by asserting the Enh input
“low”.
Table 7. Primary Register Programming
Interface
Mode
Smode
R5
R4
M8
M7
M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
Enh
Bmode
Pre_en
Parallel
1
0
0
M2_WR rising edge load
M1_WR rising edge load
A_WR rising edge load
D3
B0
D2
B1
D1
B2
D0
B3
D7
B4
D6
B5
D5
B6
D4
B7
D3
B8
D2
B9
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Serial*
Direct
1
1
0
1
1
B10
B11
B12
B13
B14
B15
B16
B17
B18 B19
A1 A0
X
0
0
0
0
Pre_en
M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode
Power
down
Counter
load
MSEL
output
Prescaler
output
Smode
Reserved
Reserved
Reserved
fc, fp OE
Enh
0
Bmode
E_WR rising edge load
Parallel
Serial*
X
X
0
1
D7
B0
D6
B1
D5
B2
D4
D3
D2
B5
D1
B6
D0
B7
0
B3
B4
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
(last in) LSB
Document No. 70-0033-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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