PFS122
8bit MTP MCU with 12-bit R-Type ADC
5.4.3. IHRC Frequency Calibration and System Clock
During compiling the user program, the options for IHRC calibration and system clock are shown as Table 3:
SYSCLK
○ Set IHRC / 2
○ Set IHRC / 4
○ Set IHRC / 8
○ Set IHRC / 16
○ Set IHRC / 32
○ Set ILRC
CLKMD
IHRCR
Calibrated
Calibrated
Calibrated
Description
= 34h (IHRC / 2)
= 14h (IHRC / 4)
= 3Ch (IHRC / 8)
IHRC calibrated to 16MHz, CLK=8MHz (IHRC/2)
IHRC calibrated to 16MHz, CLK=4MHz (IHRC/4)
IHRC calibrated to 16MHz, CLK=2MHz (IHRC/8)
IHRC calibrated to 16MHz, CLK=1MHz (IHRC/16)
IHRC calibrated to 16MHz, CLK=0.5MHz (IHRC/32)
IHRC calibrated to 16MHz, CLK=ILRC
= 1Ch (IHRC / 16) Calibrated
= 7Ch (IHRC / 32) Calibrated
= E4h (ILRC / 1)
No change
Calibrated
○ Disable
No Change IHRC not calibrated, CLK not changed
Table 3: Options for IHRC Frequency Calibration
Usually, .ADJUST_IC will be the first command after boot up, in order to set the target operating frequency
whenever starting the system. The program code for IHRC frequency calibration is executed only one time
that occurs in writing the codes into MTP memory; after then, it will not be executed again. If the different
option for IHRC calibration is chosen, the system status is also different after boot. The following shows the
status of PFS122 for different option:
(1) .ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
After boot up, CLKMD = 0x34：
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/2 = 8MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(2) .ADJUST_IC
SYSCLK=IHRC/4, IHRC=16MHz, VDD=3.3V
After boot up, CLKMD = 0x14：
IHRC frequency is calibrated to 16MHz@VDD=3.3V and IHRC module is enabled
System CLK = IHRC/4 = 4MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(3) .ADJUST_IC
SYSCLK=IHRC/8, IHRC=16MHz, VDD=2.5V
After boot up, CLKMD = 0x3C：
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/8 = 2MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
SYSCLK=IHRC/16, IHRC=16MHz, VDD=2.5V
(4) .ADJUST_IC
After boot up, CLKMD = 0x1C：
IHRC frequency is calibrated to 16MHz@VDD=2.5V and IHRC module is enabled
System CLK = IHRC/16 = 1MHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
(5) .ADJUST_IC
SYSCLK=IHRC/32, IHRC=16MHz, VDD=5V
After boot up, CLKMD = 0x7C：
IHRC frequency is calibrated to 16MHz@VDD=5V and IHRC module is enabled
System CLK = IHRC/32 = 500KHz
Watchdog timer is disabled, ILRC is enabled, PA5 is in input mode
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PDK-DS-PFS122-EN_V000-May 28, 2020
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