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OXCB950-TQAG 参数 Datasheet PDF下载

OXCB950-TQAG图片预览
型号: OXCB950-TQAG
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的高性能UART的Cardbus / 3.3V PCI接口 [Integrated High Performance UART Cardbus / 3.3v PCI interface]
分类和应用: PC
文件页数/大小: 67 页 / 598 K
品牌: OXFORD [ OXFORD SEMICONDUCTOR ]
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OXCB950  
OXFORD SEMICONDUCTOR LTD.  
7.10.4 External 1x Clock Mode  
connected to the XTLI pin. The circuit required to use the  
internal oscillator is shown in Figure 1.  
The transmitter and receiver can accept an external clock  
applied to the RI# and DSR# pins respectively. The clock  
options are selected using the CKS register (see section  
7.11.8). The transmitter and receiver may be configured to  
operate in 1x (i.e. Isochronous mode) by setting CKS[7]  
and CKS[3], respectively. In Isochronous mode, transmitter  
or receiver will use the 1x clock (usually, but not  
necessarily, an external source) where asynchronous  
framing is maintained using start-, parity- and stop-bits.  
However serial transmission and reception is synchronised  
to the 1x clock. In this mode asynchronous data may be  
transmitted at baud rates up to 60Mbps. The local 1x clock  
source can be asserted on the DTR# pin.  
XTLO  
R2  
C1  
R1  
XTLI  
C2  
Figure 1: Crystal Oscillator Circuit  
Frequency  
Range  
C1  
C2 (pF)  
R1 ()  
R2 ()  
Note that line drivers need to be capable of transmission at  
data rates twice the system clock used (as one cycle of the  
system clock corresponds to 1 bit of serial data). Also note  
that enabling modem interrupts is illegal in isochronous  
mode, as the clock signal will cause a continuous change  
to the modem status (unless masked in MDM register, see  
section 7.11.10).  
(pF)  
(MHz)  
1.8432 - 8  
8-60  
68  
22  
220k  
470R  
470R  
33-68  
33 – 68 220k-2M2  
Table 23: Component values  
Note: For better stability use a smaller value of R1.  
Increase R1 to reduce power consumption.  
7.10.5 Crystal Oscillator Circuit  
The total capacitive load (C1 in series with C2) should be  
that specified by the crystal manufacturer (nominally 16pF).  
The UARTs reference reference clock may be provided by  
its own crystal oscillator or directly from a clock source  
7.11 Additional Features  
This bit is cleared after a hardware reset or channel  
software reset. The software driver may write a 0 to this bit  
to re-enable the remote transmitter (an XON is  
transmitted). Note: writing a 1 to this bit has no effect.  
7.11.1 Additional Status Register ‘ASR’  
ASR[0]: Transmitter disabled  
logic 0 The transmitter is not disabled by in-band flow  
control.  
ASR[2]: RTS  
logic 1 The receiver has detected an XOFF, and has  
disabled the transmitter.  
This is the complement of the actual state of the RTS# pin  
when the device is not in loopback mode. The driver  
software can determine if the remote transmitter is disabled  
by RTS# out-of-band flow control by reading this bit. In  
loopback mode this bit reflects the flow control status rather  
than the pin’s actual state.  
This bit is cleared after a hardware reset or channel  
software reset. The software driver may write a 0 to this bit  
to re-enable the transmitter if it was disabled by in-band  
flow control. Writing a 1 to this bit has no effect.  
ASR[3]: DTR  
ASR[1]: Remote transmitter disabled  
logic 0 The remote transmitter is not disabled by in-  
band flow control.  
This is the complement of the actual state of the DTR# pin  
when the device is not in loopback mode. The driver  
software can determine if the remote transmitter is disabled  
by DTR# out-of-band flow control by reading this bit. In  
loopback mode this bit reflects the flow control status rather  
than the pin’s actual state.  
logic 1 The transmitter has sent an XOFF character, to  
disable the remote transmitter (cleared when  
subsequent XON is sent).  
DS-0033 Sep 05  
External-Free Release  
Page 46  
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