OXCB950
OXFORD SEMICONDUCTOR LTD.
Level 2a:
Receiver data available interrupt (ISR[5:0]=’000100’):
This interrupt is active whenever the receiver FIFO level is
above the interrupt trigger level.
7.6.2 Interrupt Status Register ‘ISR’
The source of the highest priority interrupt pending is
indicated by the contents of the Interrupt Status Register
‘ISR’. There are nine sources of interrupt at six levels of
priority (1 is the highest) as shown in Table 18.
Level 2b:
Receiver time-out interrupt (ISR[5:0]=’001100’):
A receiver time-out event, which may cause an interrupt,
will occur when all of the following conditions are true:
Level Interrupt source
ISR[5:0]
see note 3
•
•
•
The UART is in a FIFO mode
1
-
No interrupt pending
000001
000110
There is data in the RHR.
1
Receiver status error or
Address-bit detected in 9-bit mode
Receiver data available
Receiver time-out
There has been no read of the RHR for a period of
time greater than the time-out period.
2a
2b
3
000100
001100
000010
000000
•
There has been no new data written into the RHR for
a period of time greater than the time-out period. The
time-out period is four times the character period
(including start and stop bits) measured from the
centre of the first stop bit of the last data item
received.
Transmitter THR empty
Modem status change
4
2
5
In-band flow control XOFF or 010000
Special character (XOFF2) or
Special character 1, 2, 3 or 4 or
bit 9 set in 9-bit mode
Reading the first data item in RHR clears this interrupt.
2
6
CTS or RTS change of state
100000
Level 3:
Table 18: Interrupt Status Identification Codes
Transmitter empty interrupt (ISR[5:0]=’000010’):
This interrupt is set when the transmit FIFO level falls
below the trigger level. It is cleared on an ISR read of a
level 3 interrupt or by writing more data to the THR so that
the trigger level is exceeded. Note that when 16C950 mode
trigger levels are enabled (ACR[5]=1) and the transmitter
trigger level of zero is selected (TTL=0x00), a transmitter
empty interrupt will only be asserted when both the
transmitter FIFO and transmitter shift register are empty
and the SOUT line has returned to idle marking state.
Note1:
Note2:
ISR[0] indicates whether any interrupts are pending.
Interrupts of priority levels 5 and 6 cannot occur unless the
UART is in Enhanced mode.
Note3:
ISR[5] is only used in 650 & 950 modes. In 750 mode, it is ‘0’
when FIFO size is 16 and ‘1’ when FIFO size is 128. In all
other modes it is permanently set to 0
7.6.3 Interrupt Description
Level 1:
Level 4:
Receiver status error interrupt (ISR[5:0]=’000110’):
Normal (non-9-bit) mode:
Modem change interrupt (ISR[5:0]=’000000’):
This interrupt is set by a modem change flag (MSR[0],
MSR[1], MSR[2] or MSR[3]) becoming active due to
changes in the input modem lines. This interrupt is cleared
following a read of the MSR.
This interrupt is active whenever any of LSR[1], LSR[2],
LSR[3] or LSR[4] are set. These flags are cleared following
a read of the LSR. This interrupt is masked with IER[2].
9-bit mode:
This interrupt is active whenever any of LSR[1], LSR[2],
LSR[3] or LSR[4] are set. The receiver error interrupt due
to LSR[1], LSR[3] and LSR[4] is masked with IER[3]. The
‘address-bit’ received interrupt is masked with NMR[1]. The
software driver can differentiate between receiver status
Level 5:
Receiver in-band flow control (XOFF) detect interrupt,
Receiver special character (XOFF2) detect interrupt,
Receiver special character 1, 2, 3 or 4 interrupt or
th
th
9 Bit set interrupt in 9-bit mode (ISR[5:0]=’010000’):
error and received address-bit (9 data bit) interrupt by
A level 5 interrupt can only occur in Enhanced-mode when
any of the following conditions are met:
examining LSR[1] and LSR[7]. In 9-bit mode LSR[7] is only
set when LSR[3] or LSR[4] is set and it is not affected by
th
LSR[2] (i.e. 9 data bit).
•
•
•
A valid XOFF character is received while in-band flow
control is enabled.
A received character matches XOFF2 while special
character detection is enabled, i.e. EFR[5]=1.
A received character matches special character 1, 2, 3
or 4 in 9-bit mode (see section 7.11.9).
It is cleared on an ISR read of a level 5 interrupt.
External-Free Release
DS-0033 Sep 05
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