OX16C950 rev B
OXFORD SEMICONDUCTOR LTD.
RESET CONFIGURATION
7
7.1
Hardware Reset
7.2
Software Reset
After a hardware reset, all writable registers are reset to
0x00, with the following exceptions:
An additional feature available in the OX16C950 device is
software resetting of the serial channel. The software reset
is available using the CSR register. Software reset has the
same effect as a hardware reset except it does not reset
the clock source selections (i.e. CKS register and CKA
register). To reset the UART write 0x00 to the Channel
Software Reset register ‘CSR’.
1. DLL which is reset to 0x01.
2. MCR[7] is reset to the complement of the CLKSEL
input pin value (see section 11.1).
3. CPR is reset to 0x20.
The state of read-only registers following a hardware reset
is as follows:
RHR[7:0]: Indeterminate
RFL[6:0]: 00000002
TFL[6:0]: 00000002
LSR[7:0]: 0x60 signifying that both the transmitter and the
transmitter FIFO are empty
MSR[3:0]: 00002
MSR[7:4]: Dependent on modem input lines DCD, RI, DSR
and CTS respectively
ISR[7:0]: 0x01, i.e. no interrupts are pending
ASR[7:0]: 1xx000002
RFC[7:0]: 000000002
GDS[7:0]: 000000012
DMS[7:0]: 000000102
CKA[7:0]: 000000002
The reset state of output signals for are tabulated below:
Signal
SOUT
RTS#
DTR#
INT
Reset state
Inactive High
Inactive High
Inactive High
Inactive low when INTSEL# pin is high or
floating, otherwise high-impedance
Inactive High
RXRDY#
TXRDY#
Active low (THR is able to receive data).
Table 8: Output Signal Reset State
Data Sheet Revision 1.2
Page 19
OXFORD [ OXFORD SEMICONDUCTOR ]
