RSL10
Table 9. CHIP INTERFACE SPECIFICATIONS
Power
Domain
Pad #,
WLCSP
Pad #,
QFN48
Pad Name
NRESET
WAKEUP
VDDC
Description
I/O
I
A/D
D
Pull
Reset pin
VDDO
U
L9
L8
16
15
19
21
36
28, 35
42
31
18
20
23
25
24
27
29
30
26
22
32
38
37
39
41
40
33
34
Wake−up pin for power modes
LDO output for Core logic voltage supply
LDO output for memories voltage supply
Digital I/O voltage supply
Digital ground pad for I/O
Substrate connection for the RF part
External clock input
I
A
I/O
I/O
I
P
H6
F4
VDDM
VDDO
P
P
B4
VSSD
I/O
I/O
I
P
F3, D6, F9
B6
VSS (*)
EXTCLK
DIO[0]
P
D
U
F1
Digital input output / ADC 0
Digital input output / ADC 1
Digital input output / ADC 2
Digital input output / ADC 3
Digital input output 4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A/D
A/D
A/D
A/D
D
U/D
U/D
U/D
U/D
U/D
U/D
U/D
U/D
U/D
U/D
U/D
U/D
U/D
U/D
U/D
U/D
U
L4
DIO[1]
L3
DIO[2]
L2
DIO[3]
L1
DIO[4]
K2
DIO[5]
Digital input output 5
D
K1
DIO[6]
Digital input output 6
D
J1
DIO[7]
Digital input output 7
D
H1
G2
E2
DIO[8]
Digital input output 8
D
DIO[9]
Digital input output 9
D
DIO[10]
DIO[11]
DIO[12]
DIO[13]
DIO[14]
DIO[15]
JTCK
Digital input output 10
D
D1
B2
Digital input output 11
D
Digital input output 12
D
A1
Digital input output / CM3−JTAG Test Reset
Digital input output / CM3−JTAG Test Data In
D
A2
D
A3
Digital input output / CM3−JTAG Test Data Out
CM3−JTAG Test Clock
D
A4
D
C1
B1
JTMS
CM3−JTAG Test Mode State
D
U
*VSS should be connected to VSSRF at the PCB level.
Legend:
Type: A = analog; D = digital; I = input; O = output; P = power
Pull: U = pull up; D = pull down
Pull up: selectable between 10 kW and 250 kW
Pull down: 250 kW
All digital pads have a Schmitt trigger input.
2
All DIO pads have a programmable I C low pass filter.
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