NCP5392P
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < T < 85°C; 4.75 V < V < 5.25 V; All DAC Codes; C
= 0.1 mF)
A
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
VR_RDY (POWER GOOD) OUTPUT
VR_RDY High – Output Leakage
Current (Note 3)
VR_RDY = 5.5 V via 1 K
-
-
-
0.2
mA
VR_RDY Upper Threshold Voltage
VCore Increasing, DAC = 1.3 V
310
270
mV
Below
DAC
VR_RDY Lower Threshold Voltage
VCore Decreasing
DAC = 1.3 V
410
370
mV
Below
DAC
VR_RDY Rising Delay
VR_RDY Falling Delay
PWM OUTPUTS
VCore Increasing
VCore Decreasing
-
-
500
5
-
-
ms
ms
Output High Voltage
Mid Output Voltage
Sourcing 500 mA
Sinking 500 mA
3.0
1.4
-
-
1.5
-
-
V
V
1.6
0.7
15
Output Low Voltage
Delay + Fall Time (Note 3)
V
C (PCB) = 50 pF,
L
DVo = V to GND
-
10
ns
CC
Delay + Rise Time (Note 3)
C (PCB) = 50 pF,
L
DVo = GND to V
-
-
10
75
15
-
ns
CC
Output Impedance – HI or LO State
Resistance to V (HI) or GND
CC
(LO)
W
2/3/4-PhASE DETECTION
Gate Pin Source Current
Gate Pin Threshold Voltage
Phase Detect Timer
60
210
15
80
240
20
150
265
27
mA
mV
ms
DIGITAL SOFT-START
Soft-Start Ramp Time
VR11 Vboot time
DAC = 0 to DAC = 1.1 V
1.0
-
1.5
ms
400
500
600
ms
VID7/VR11/AMD INPUT
VID Upper Threshold
VID Lower Threshold
VID Hysteresis
V
V
V
-
450
-
650
550
100
-
770
-
mV
mV
mV
mA
UPPER
LOWER
UPPER
- V
-
LOWER
AMD Input Bias Current
VR11 Input Bias Current (Note 3)
10
20
200
300
nA
ns
Delay before Latching VID Change
(VID De-Skewing) (Note 3)
Measured from the edge of the
st
200
-
1
VID change
AMD Upper Threshold (Note 3)
AMD Lower Threshold (Note 3)
ENABLE INPUT
2.9
V
V
2.4
-
Enable High Input Leakage Current
(Note 3)
Pullup to 1.3 V
-
200
nA
VR11 Rising Threshold
VR11 Falling Threshold
VR11 Total Hysteresis
AMD Upper Threshold
AMD Lower Threshold
-
450
-
650
550
100
1.3
770
-
mV
mV
mV
V
Rising- Falling Threshold
-
-
1.5
-
0.9
1.1
V
3. Guaranteed by design, not tested in production.
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