MC74VHCT157A
S
A0
B0
Y0
A1
B1
Y1
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
E
A3
B3
Y3
A2
B2
Y2
Figure 1. Pin Assignment
A0
B0
A1
B1
A2
B2
A3
B3
E
S
2
3
5
6
11
10
14
13
15
1
12 Y3
9 Y2
7
Y1
DATA
OUTPUTS
4
Y0
NIBBLE
INPUTS
Figure 2. Expanded Logic Diagram
E
S
A0
B0
A1
B1
A2
B2
A3
B3
15
1
2
3
5
6
11
10
14
13
EN
G1
1
1
MUX
4
7
9
12
Y0
Y1
Y2
Y3
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications
of any voltage higher than maximum rated
voltages to this high−impedance circuit. For
proper operation, V
in
and V
out
should be
constrained to the range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
GND or V
CC
). Unused outputs must be left
open.
Figure 3. IEC Logic Symbol
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