MC100EL39
V
Q0
Q0 Q1 Q1
18 17 16
Q2 Q2 Q3 Q3
V
EE
CC
Table 1. PIN DESCRIPTION
Pin
20
19
15
14
13
12
11
Function
CLK, CLK
EN
MR
ECL Diff Clock Inputs
ECL Sync Enable
ECL Master Reset
Q0, Q0; Q1, Q1
Q2, Q2; Q3, Q3
DIVSELa,
DIVSELb
ECL Diff ÷2/4 Outputs
ECL Diff ÷4/6 Outputs
ECL Frequency Select Input
ECL Frequency Select Input
Reference Voltage Output
Positive Supply
1
2
3
4
5
6
7
8
9
10
V
EN
CLK CLK
V
MR
V
CC
NC
CC
BB
V
V
V
BB
CC
EE
Negative Supply
NC
No Connect
NOTE: All V pins are tied together on the die.
CC
Warning: All V and V pins must be externally connected to
CC
EE
Power Supply to guarantee proper operation.
Figure 1. Pinout: SOIC−20 (Top View)
Table 2. FUNCTION TABLE
Function
CLK*
EN*
MR*
DIVSELa
Divide
Z
ZZ
X
L
H
X
L
L
H
Q0
Hold Q
0−3
0−3
CLK
CLK
P2/4
R
Reset Q
Q0
Q1
Z = Low-to-High Transition
ZZ = High-to-Low Transition
*Pin will default low when left open.
Q1
Q2
DIVSELa**
Q , Q Outputs
0 1
EN
P4/6
0
1
Divide by 2
Divide by 4
Q2
Q3
R
DIVSELb**
Q , Q Outputs
2 3
MR
Q3
0
1
Divide by 4
Divide by 6
DIVSELb
**Pin will default low when left open.
Figure 2. Logic Diagram
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