MC100EL39
5VꢀECL ÷2/4, ÷4/6 Clock
Generation Chip
The MC100EL39 is a low skew ÷2/4, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned.
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The V pin, an internally generated voltage supply, is available to
BB
this device only. For single-ended input conditions, the unused
differential input is connected to V as a switching reference voltage.
BB
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
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The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon startup, the internal flip-flops will attain a random state;
therefore, for systems which utilize multiple EL39s, the Master Reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EL39, the MR pin need not be exercised as the
internal divider design ensures synchronization between the ÷2/4 and
the ÷4/6 outputs of a single device.
SO−20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100EL39
AWLYYWWG
Features
• 50 ps Output-to-Output Skew
• Synchronous Enable/Disable
1
• Master Reset for Synchronization
• ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V = 4.2 V to 5.7 V with V = 0 V
CC
EE
• NECL Mode Operating Range: V = 0 V with
CC
*For additional marking information, refer to
Application Note AND8002/D.
V
= −4.2 V to −5.7 V
EE
• Internal Input Pulldown Resistors on EN, MR, CLK(s), and
DIVSEL(s)
• Q Output will Default LOW with Inputs Open or at V
EE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index 28 to 34
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
• Transistor Count = 419 devices
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 6
MC100EL39/D
ONSEMI [ ONSEMI ]
