CAT93C86
Erase
Erase All
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking of
the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the CAT93C86
can be determined by selecting the device and polling the
DO pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of t . The falling
CSMIN
t
edge of CS will start the self clocking clear cycle of all
memory locations in the device. The clocking of the SK pin
is not necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to a
logical “1” state.
CSMIN
Erase/Write Enable and Disable
Write All
The CAT93C86 powers up in the write disable state. Any
writing after power−up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled, it
will remain enabled until power to the device is removed, or
the EWDS instruction is sent. The EWDS instruction can be
used to disable all CAT93C86 write and clear instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status.
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
. The falling edge of CS will start the self clocking
CSMIN
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C86 can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
SK
CS
STANDBY
STATUS
VERIFY
t
CS
A
N
A
N−1
A
0
DI
1
1
1
t
t
SV
HZ
HIGH−Z
BUSY
DO
READY
HIGH−Z
t
EW
Figure 5. Erase Instruction Timing
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