CAT93C86
t
t
t
SKHI
SKLOW
CSH
SK
t
t
DIH
DIS
VALID
VALID
DI
t
CSS
CS
t
, t
t
CSMIN
t
PD0 PD1
DIS
DO
DATA VALID
Figure 2. Synchronous Data Timing
SK
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
CS
DI
Don’t Care
A
N
A
A
N−1
0
1
HIGH−Z
DO
Dummy 0
D
D
0
Address + 1 Address + 2 Address + n
15 . . .
or
D
D
0
D
D
0
D
15 . . .
15 . . .
15 . . .
D
D
0
or
or
or
7 . . .
D
D
0
D
D
0
D
7 . . .
7 . . .
7 . . .
Figure 3. Read Instruction Timing
SK
t
CSMIN
STANDBY
CS
DI
STATUS
VERIFY
A
N
A
N−1
A
0
D
D
0
N
1
0
1
t
SV
t
HZ
BUSY
HIGH−Z
DO
READY
HIGH−Z
t
EW
Figure 4. Write Instruction Timing
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