Connection Diagrams
Pin Descriptions
Pin Assignment for SSOP and TSSOP
Pin Names
Description
OEn
Output Enable Input (Active LOW)
I0–I15
O0–O15
NC
Inputs
Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
O0
O2
NC
O1
OE1
NC
OE2
NC
NC
I1
I0
I2
O4
O3
VCC
VCC
I3
I4
O6
O5
GND GND
GND GND
GND GND
I5
I6
O8
O7
I7
I8
O10
O12
O14
O9
I9
I10
I12
I14
G
H
O11
O13
VCC
NC
VCC
NC
I11
I13
J
O15
NC
OE4
OE3
NC
I15
Truth Tables
Inputs
OE1
Outputs
O0–O3
I0–I3
L
L
L
H
X
L
H
Z
Pin Assignment for FBGA
H
Inputs
OE2
Outputs
O4–O7
I4–I7
L
L
L
H
X
L
H
Z
H
Inputs
OE3
Outputs
O8–O11
I8–I11
(Top Thru View)
L
L
L
H
X
L
H
Z
H
Inputs
OE4
Outputs
O12–O15
I12–I15
L
L
L
H
X
L
H
Z
H
H
L
HIGH Voltage Level
LOW Voltage Level
X
Z
Immaterial
High Impedance
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