KAI−04070
Reset Pin, Low Gain (R2ab and R2cd)
The R2ab and R2bc (pins 17 and 51) each have an internal
circuit to bias the pins to 4.3 V. This feature assures the
device is set to operate in the high gain mode when pins 17
and 51 are not connected in the application to a clock driver
(for KAI−08050 compatibility). Typical capacitor coupled
drivers will not drive this structure.
VDD
(+15 V)
VDD
(+15 V)
R2
4.3 V
68 kW
20 kW
68 kW
20 kW
27 kW
27 kW
GND
GND
Figure 23. Equivalent Circuit for Reset Gate, Low Gain (R2ab and R2cd)
Power-Up and Power-Down Sequence
Adherence to the power-up and power-down sequence is
critical. Failure to follow the proper power-up and
power-down sequences may cause damage to the sensor.
Do Not Pulse the Electronic Shutter until ESD is Stable
V+
VDD
SUB
Time
HCCD
Low
VCCD
Low
ESD
V−
Activate All Other Biases when ESD is Stable and Sub is above 3 V
Notes:
1. Activate all other biases when ESD is stable and SUB is above 3 V.
2. Do not pulse the electronic shutter until ESD is stable.
3. VDD cannot be +15 V when SUB is 0 V.
4. The image sensor can be protected from an accidental improper ESD voltage by current limiting the SUB current to less than 10 mA. SUB
and VDD must always be greater than GND. ESD must always be less than GND. Placing diodes between SUB, VDD, ESD and ground
will protect the sensor from accidental overshoots of SUB, VDD and ESD during power on and power off. See the figure below.
Figure 24. Power-Up and Power-Down Sequence
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