KAI−04070
AC Operating Conditions
Table 15. CLOCK LEVELS
Pins
(Note 1)
Description
Symbol
V1_L
Level
Low
Mid
Min.
−8.2
−0.2
11.5
−8.2
−0.2
−8.2
−0.2
−8.2
−0.2
−5.2
3.8
Nom.
−8.0
0.0
Max.
−7.8
0.2
Unit
Vertical CCD Clock, Phase 1
V1B, V1T
V
V1_M
V1_H
V2_L
High
Low
High
Low
High
Low
High
Low
12.0
−8.0
0.0
12.5
−7.8
0.2
Vertical CCD Clock, Phase 2
V2B, V2T
V3B, V3T
V4B, V4T
H1Sa
V
V
V
V
V
V
V
V
V
V
V
V2_H
V3_L
Vertical CCD Clock, Phase 3
−8.0
0.0
−7.8
0.2
V3_H
V4_L
Vertical CCD Clock, Phase 4
−8.0
0.0
−7.8
0.2
V4_H
H1S_L
Horizontal CCD Clock, Phase 1 Storage
Horizontal CCD Clock, Phase 1 Barrier
Horizontal CCD Clock, Phase 2 Storage
Horizontal CCD Clock, Phase 2 Barrier
−4.0
4.0
−3.8
5.2
H1S_A
H1B_L
H1B_A
H2S_L
H2S_A
H2B_L
H2B_A
H2SL_L
H2SL_A
R_L
Amplitude (Note 3)
Low
H1Ba
−5.2
3.8
−4.0
4.0
−3.8
5.2
Amplitude (Note 3)
Low
H2Sa
−5.2
3.8
−4.0
4.0
−3.8
5.2
Amplitude (Note 3)
Low
H2Ba
−5.2
3.8
−4.0
4.0
−3.8
5.2
Amplitude (Note 3)
Low
Horizontal CCD Clock, Last Phase
(Note 2)
H2SLa
R1a
−5.2
4.8
−5.0
5.0
−4.8
5.2
Amplitude (Note 3)
Low
Reset Gate
−3.2
6.0
−3.0
−
−2.8
6.4
R_A
Amplitude
Low
Reset Gate 2
R2a
R2_L
−2.0
6.0
−1.8
−
−1.6
6.4
R2_A
Amplitude
High
Electronic Shutter (Note 4)
SUB
VES
29.0
30.0
40.0
1. a denotes a, b, c or d.
2. Use separate clock driver for improved speed performance.
3. The horizontal clock amplitude should be set such that the high level reaches 0.0 V. Examples:
a. If the minimum horizontal low voltage of −5.2 V is used, then a 5.2 V amplitude clock is required for a clock swing of −5.2 V to 0.0 V.
b. If the maximum horizontal low voltage of −3.8 V is used, then a 3.8 V amplitude clock is required for a clock swing of −3.8 V to 0.0 V.
4. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock
are referenced to ground.
VES
VSUB
GND
GND
Figure 28. DC Bias and AC Clock Applied to the SUB Pin
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