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ML87V21071TB 参数 Datasheet PDF下载

ML87V21071TB图片预览
型号: ML87V21071TB
PDF下载: 下载PDF文件 查看货源
内容描述: [Consumer Circuit, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100]
分类和应用: 商用集成电路
文件页数/大小: 123 页 / 812 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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PEDL87V21071-01  
OKI Semiconductor  
ML87V21071  
PIN DESCRIPTIONS  
Termination of  
unused pin  
No.  
Symbol  
I/O  
Pad Remarks  
Pin Description  
1
2
N.C.  
VSS  
Unused pin  
Ground  
Not used  
X
Schmitt(IN)/  
OpenDrain(OUT)  
Schmitt  
3
4
5
SDA  
SCL  
I/O  
I2C-bus data pin  
I2C-bus clock pin  
X
I
I
X
Schmitt  
Not used or  
connected to GND  
SLA1  
Slave address setting pin bit 1  
Slave address setting pin bit 2  
pull-down 50k  
Schmitt  
Not used or  
connected to GND  
6
SLA2  
I
pull-down 50k  
7
YI7  
YI6  
YI5  
YI4  
YI3  
YI2  
YI1  
YI0  
VDD  
ICLK  
VSS  
I
I
Luminance signal input pin bit 7 (MSB)  
Luminance signal input pin bit 6  
Luminance signal input pin bit 5  
Luminance signal input pin bit 4  
Luminance signal input pin bit 3  
Luminance signal input pin bit 2  
Luminance signal input pin bit 1  
Luminance signal input pin bit 0 (LSB)  
3.3 V power supply  
X
X
X
X
X
X
X
X
X
X
X
8
9
I
10  
11  
12  
13  
14  
15  
16  
17  
I
I
I
I
I
I
System clock Input pin  
Ground  
Not used or  
connected to GND  
18  
19  
20  
21  
22  
23  
24  
25  
CI7  
CI6  
CI5  
CI4  
CI3  
CI2  
CI1  
CI0  
I
I
I
I
I
I
I
I
pull-down 50k Chrominance signal input pin bit 7 (MSB)  
pull-down 50k Chrominance signal input pin bit 6  
pull-down 50k Chrominance signal input pin bit 5  
pull-down 50k Chrominance signal input pin bit 4  
pull-down 50k Chrominance signal input pin bit 3  
pull-down 50k Chrominance signal input pin bit 2  
pull-down 50k Chrominance signal input pin bit 1  
pull-down 50k Chrominance signal input pin bit 0 (LSB)  
Not used or  
connected to GND  
Not used or  
connected to GND  
Not used or  
connected to GND  
Not used or  
connected to GND  
Not used or  
connected to GND  
Not used or  
connected to GND  
Not used or  
connected to GND  
26  
27  
28  
VDD  
N.C.  
VSS  
3.3 V power supply  
Unused pin  
X
Not used  
X
Ground  
Schmitt  
Not used or  
connected to GND  
29  
30  
31  
IVS  
IHS  
I
I
I
Input system vertical Sync. signal input pin  
pull-down 50k  
Schmitt  
Not used or  
connected to GND  
Input system horizontal Sync. signal input pin  
pull-down 50k  
Schmitt  
pull-down 50k  
Schmitt  
Mode setting pin bit 0  
(Equivalent to internal register VMD[0])  
Not used or  
connected to GND  
MODE0  
Mode setting pin bit 1  
(Equivalent to internal register HMD[0])  
Not used or  
connected to GND  
32  
33  
MODE1  
N.C.  
I
pull-down 50k  
Unused pin  
Not used  
4/123  
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