PEDL87V21071-01
OKI Semiconductor
ML87V21071
1.2.2 Output Data Format
Since internal signal processing is performed independently for luminance and chrominance signals, the output
data format of basic output of this IC is YCbCr 16bit 4:2:2.
However, in YCbCr 8bit 4:2:2 mode and ITU-R BT.656 mode, selection of YCbCr 8bit 4:2:2 (same format as
input) is enabled by setting DOSEL (SUB:60h-bit[1]) to 1. In this case, unused CO[7:0] becomes Hi-Z.
Table F1-2-2(2) shows the delay amount from input to output and the same delay amount occurs for all the data
and Sync. signals.
Table F1-2-2 (1) Output Data Format
Output
YO7
YO6
YO5
YO4
YO3
YO2
YD1
YD0
CO7
CO6
CO5
CO4
CO3
CO2
CO1
CO0
Normal mode
8-bit input – 8-bit output mode (DOSEL =1)
Y07
Y06
Y07
Y06
Cr07
Cr06
Cr05
Cr04
Cr03
Cr02
Cr01
Cr00
—
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
—
Cb07
Cb06
Cb05
Cb04
Cb03
Cb02
Cb01
Cb00
—
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
—
Y05
Y05
Y04
Y04
Y03
Y03
Y02
Y02
Y01
Y01
Y00
Y00
Cb07
Cb06
Cb05
Cb04
Cb03
Cb02
Cb01
Cb00
Cr07
Cr06
Cr05
Cr04
Cr03
Cr02
Cr01
Cr00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table F1-2-2(2) Combinations for Input/Output Data Format
DISEL
R656I
DOSEL
Input
Output
Input/output delay
amount
0
1
1
X
X
0
0
0
1
1
X
0
1
0
1
16-bit + Sync (H, V)
8-bit + Sync (H, V)
8-bit + Sync (H, V)
ITU-R BT.656
16-bit + Sync (H, V)
8-bit + Sync (H, V)
32 (ICLK)
64 (ICLK)
66 (ICLK)
64 (ICLK)
66 (ICLK)
8-bit + Sync (H, V)
16-bit + Sync (H, V)
ITU-R BT.656 + Sync (H, V)
ITU-R BT.656
* When input is ITU-R BT.656, Sync (H, V) on the output side is output to OVS and OHS as the Sync. signal
separated from SAV and EAV.
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