PEDL87V21071-01
OKI Semiconductor
ML87V21071
• Internal Input System Clock (IICLK)
The IICLK is IICLK = ICLK in 16-bit 4:2:2 mode whereas in 8-bit 4:2:2 mode and ITU-R BT.656 mode
it is the clock pulse obtained by internally frequency-dividing ICLK to 1/2.
In 8-bit 4:2:2 mode, the position which is two ICLK clocks delayed from the rise of IHS is used for
resetting and IICLK is generated by frequency-dividing ICLK to 1/2.
Normally reset of IICLK presumes the rise position of positive polarity IHS (IHSINV = 0), but by setting
IHES (SUB:41h-bit[5]) and IHSINV, selection of compliance with negative polarity IHS and fall
position is also possible.
In ITU-R BT 656 mode, ICLK is frequency-divided to 1/2 based on SAV.
In 8-bit 4:2:2 mode, if the phase of IHS for luminance and chrominance data reverses (number of ICLKs
from IICLK reset to initial chrominance data is odd), it is possible to avoid the reversal by setting ICINV
(SUB:41h-bit[4]).
Table F1-2-1 (3) IICLK Reset Position
IHES
0
IHSINV
Reset position
Positive polarity IHS rise (horizontal Sync. signal front
edge)
0
Positive polarity IHS fall (horizontal Sync. signal rear
edge)
1
0
1
0
1
1
Negative polarity IHS fall (horizontal Sync. signal front
edge)
Negative polarity IHS rise (horizontal Sync. signal rear
edge)
Table F1-2-1 (4) Compliance with Luminance-Chrominance Phase Reversal
ICINV
Usage conditions (8-bit 4:2:2 mode)
0
1
Number of ICLKs from IICLK reset to initial chrominance data is even.
Number of ICLKs from IICLK reset to initial chrominance data is odd.
8-bit 4:2:2 mode
ICLK
IHS
IICLK
Reset
IICLK
Crn
Yn
Cbn
Yn+1
YI[7:0]
Figure F1-2-1 (2) IICLK Phase Timing Example
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