FEDL7033-02
ML7033
1
Semiconductor
CR5 (CH1 transmit/receive level control)
B7
LV1R3
0
B6
LV1R2
0
B5
LV1R1
0
B4
LV1R0
0
B3
LV1X3
0
B2
LV1X2
0
B1
LV1X1
0
B0
LV1X0
0
CR5
default
B7 to B4
B3 to B0
… Level setting for CH1 on its receive side
The LV1R3 to LV1R0 bits determine the level for the CH1 receive side as shown in Table
9.
… Level setting for CH1 on its transmit side
The LV1X3 to LV1X0 bits determine the level for the CH1 transmit side as shown in Table
9.
Table 9 Receive and Transmit Level Setting
LV1R3/LV1X3
LV1R2/ LV1X2 LV1R1/LV1X1 LV1R0/LV1X0
Level (dBm0)
0.0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
–1.0
–2.0
–3.0
–4.0
–5.0
–6.0
–7.0
–8.0
–9.0
–10.0
–11.0
–12.0
–13.0
–14.0
OFF
31/51
OKI [ OKI ELECTRONIC COMPONETS ]
