FEDL7033-02
ML7033
1
Semiconductor
TIMING DIAGRAM
Transmit Timing - 8-bit PCM Mode with LIN (CR0-B3) bit = “0”
Long Frame Sync Mode with SHORT (CR0-B4) bit = “0”
MCK
tMB
3
BCLK
1
2
4
5
6
7
8
tXS
tSX
XSYNC
PCMOUT
PCMOSY
tWS
tXD2
D4
tXD1
tXD3
tSD
MSD
D2
D3
D5
D6
D7
D8
tXD4
Short Frame Sync Mode with SHORT (CR0-B4) bit = “1”
MCK
tMB
3
BCLK
1
2
4
5
6
7
8
tSX
tXS
XSYNC
PCMOUT
PCMOSY
tXD2
D3
tWS
tXD3
tXD1
MSD
D2
D4
D5
D6
D7
D8
tXD4
Figure 1 Transmit Side Timing Diagram
Receive Timing - 8-bit PCM Mode with LIN (CR0-B3) bit = “0”
Long Frame Sync Mode with SHORT (CR0-B4) bit = “0”
MCK
tMB
1
2
3
4
5
6
7
8
BCLK
tRS
tSR
RSYNC
PCMIN
tW S
tDS
tDH
MSD
D2
D3
D4
D5
D6
D7
D8
Short Frame Sync Mode with SHORT (CR0-B4) bit = “1”
MCK
tMB
1
2
3
4
5
6
7
8
BCLK
tSR
tRS
RSYNC
PCMIN
tW S
tDS
tDH
MSD
D2
D3
D4
D5
D6
D7
Figure 2 Receive Side Timing Diagram
Note: The above timings are also valid in 14-bit linear PCM Mode with the LIN (CR0-B3) bit = “1”,
except that the number of data bits on the PCMIN and PCMOUT signals changes from 8 to 14.
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