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ML7022-01MB 参数 Datasheet PDF下载

ML7022-01MB图片预览
型号: ML7022-01MB
PDF下载: 下载PDF文件 查看货源
内容描述: 单轨双通道PCM编解码器 [Single Rail Dual Channel PCM CODEC]
分类和应用: 解码器编解码器电信集成电路电信电路光电二极管PC
文件页数/大小: 20 页 / 119 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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FEDL7022-01-06  
1
Semiconductor  
ML7022-01  
AG  
Ground for the analog signal circuits.  
DG  
Ground for the digital signal circuits.  
This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed  
circuit board to make a common analog ground.  
SGC  
Used to generate the signal ground voltage level, by connecting a bypass capacitor. Connect a 0.1 µF capacitor  
with excellent high frequency characteristics between the AG pin and the SGC pin.  
During power down mode, this outputs are at the voltage level of AG with about 50 kimpedance.  
MCK  
Master clock input.  
The frequency must be 4.096 MHz.  
BCLK  
Shift clock signal input for the DIN and DOUT signals.  
The frequency, equal to the data rate, is 256 k to 4096 kHz. This signal must be synchronized in phase with the  
MCK (generated from the same clock source as MCK). Figure 1 shows the phase difference of MCK and BCLK.  
RSYNC  
Receive synchronizing signal input.  
Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in  
phase with the MCK (generated from the same clock source as MCK).  
XSYNC  
Transmit synchronizing signal input.  
The PCM output signal from the DOUT pin is output in synchronization with this transmit synchronizing signal.  
This synchronizing signal synchronizes all timing signals of all section. This signal must be synchronized in phase  
with the MCK (generated from the same clock source as MCK).  
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