FEDL7022-01-06
1
Semiconductor
ML7022-01
Table 2 Condition of DOUT by the Power Control
PDN CPD1 CPD2
CH1 PCM Data
H
CH2 PCM Data
H
CH1 Echo Bit
H
CH2 Echo Bit
H
0
1
1
1
1
0/1
0
0/1
0
11111111
Operate
11111111
Operate
11111111
11111111
Operate
Operate
1
0
Latched Data
Latched Data
0
1
1
1
Table 3 Condition of the Latched Output by the Power Control
PDN CPD1 CPD2
LIN
0
C1A, C2A, C3A
C1B, C2B, C3B
0
1
0/1
0/1
0/1
0/1
0/1
0/1
L
L
Latched Data
L
Latched Data
L
0/1
1
Table 4 Condition of the Analog Output by the Power Control
PDN CPD1 CPD2
GSX1
GSX2
AOUT1
AOUT2
SGC
*5
High
Impedance
High
Impedance
High
Impedance
High
Impedance
0
1
1
0/1
0
0/1
0
High
Impedance
High
Impedance
High
Impedance
High
Impedance
Operate
Operate
High
Impedance
High
Impedance
1
0
Operate
Operate
High
Impedance
High
Impedance
1
1
0
1
1
1
Operate
Operate
Operate
Operate
Operate
Operate
Operate
Operate
*5 The voltage level of AG with about 50 kΩ
16/20
OKI [ OKI ELECTRONIC COMPONETS ]
