FEDL7022-01-06
1
Semiconductor
ML7022-01
TIMING DIAGRAM
MCK
BCLK
XSYNC
DOUT
T
XS
T
XD1
1
2
T
SX
T
WS
T
SD
MSD
D2
T
XD2
D4
T
MB
3
4
5
6
7
8
D3
D5
D6
D7
D8
Figure 1 Transmit Side Timing Diagram
MCK
BCLK
T
RS
RSYNC
DIN
MSD
1
2
T
SR
T
WS
T
DS
D2
T
DH
D4
T
MB
3
4
5
6
7
8
D3
D5
D6
D7
D8
Figure 2 Receive Side Timing Diagram
1
9
17
25
1
BCLK
XSYNC
MSD
D2
D3
D4
D5
D6
D7
D8
EPD1
EC3A
EC2A
EC1A
MSD
D2
D3
D4
D5
D6
D7
D8
EPD2
EC3B
EC2B
EC1B
MSD
D2
D3
1
MSD
D2
D3
DOUT
CH1 PCM DATA ECHO bits
CH2 PCM DATA ECHO bits
Figure 3 Transmit Side Bit Configuration
1
9
17
25
BCLK
RSYNC
MSD
D2
D3
D4
D5
D6
D7
D8
CPD1
C3A
C2A
C1A
MSD
D2
D3
D4
D5
D6
D7
D8
CPD2
C3B
C2B
C1B
DIN
CH1 PCM DATA
Latch Data
CH2 PCM DATA
Latch Data
CH1 power down control bit
CH2 power down control bit
Figure 4 Receive Side Bit Configuration
9/20
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