FEDL7022-01-06
1
Semiconductor
ML7022-01
C1A, C2A, C3A, C1B, C2B, C3B
General-purpose latched output signal.
C1A, C2A, C3A, C1B, C2B, C3B bits of DIN are latched using internal timing.
These outputs can drive a LSTTL/CMOS device without external resistor.
PDN
Power down control signal.
When PDN is at logic “0” level, both Channel 1 and Channel 2 circuits are in the power down state. Also, all
internal latches are in initial state (logic “0” level).
TEST1, TEST2, TEST3, TEST4, TEST5, TEST6
These pins are used for device test.
These device test pin must be connected to the AG pin.
15/20