PEDL60851C-02
ML60851C
¡ Semiconductor
DMA Transfer Timing (4)
ML60851C to Memory (Demand Transfer, Dual Address Mode)
Parameter
DREQ Disable Time
CS Hold Time
Symbol
Condition
Min.
—
0
Max.
20
Unit
ns
Note
t1
t2
t3
t4
Load 20 pF
—
ns
Read Data Delay Time
Data Hold Time
Load 20 pF
Load 20 pF
8-bit DMA
16-bit DMA
—
0
25
ns
1
25
ns
63
105
—
ns
2
3
Recovery Time
t5
—
ns
Notes: 1. When in Dual Address mode, the DACK is ignored.
t is defined depending on CS or RD which becomes active last.
3
A7:A0 specifies the FIFO address.
Refer to READ Timing (1) for Address Setup Time and Address Hold Time.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
A7:A0
DREQ
CS
t
1
t5
t2
RD
t4
Last Packet Read
t3
DOUT
55/67
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