PEDL60851C-02
ML60851C
¡ Semiconductor
DMA Transfer Timing (1)
ML60851C to Memory (Single Transfer, Single Address Mode)
Parameter
DREQ Disable Time
DREQ Enable Time
DACK Hold Time
Symbol
Condition
Min.
—
—
0
Max.
20
Unit
ns
Note
t1
t2
t3
t4
t5
Load 20 pF
63
ns
4
1
—
ns
Read Data Delay Time
Data Hold Time
Load 20 pF
Load 20 pF
8-bit DMA
16-bit DMA
—
0
25
ns
25
ns
63
105
—
ns
2
3
Recovery Time
t6
—
ns
Notes: 1. When in Single Address mode, CS and A7:A0 are ignored.
t and t are defined depending on DACK or RD which becomes active last.
1
4
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
4. It is possible to increase t by setting the DMA interval register (DMAINTVL).
2
DREQ
t3
t2
t1
DACK
t4
t6
RD
t5
DOUT
DATA OUT
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