PEDL60851C-02
ML60851C
¡ Semiconductor
DMA Transfer Timing (2)
ML60851C to Memory (Single Transfer, Dual Address Mode)
Parameter
DREQ Disable Time
DREQ Enable Time
Read Data Delay Time
Data Hold Time
Symbol
Condition
Min.
—
Max.
20
Unit
ns
Note
t1
t2
t3
t4
Load 20 pF
—
63
ns
4
1
Load 20 pF
Load 20 pF
8-bit DMA
16-bit DMA
—
25
ns
0
25
ns
63
—
ns
2
3
Recovery Time
t5
105
—
ns
Notes: 1. When in Dual Address mode, the DACK is ignored.
t and t are defined depending on CS or RD which becomes active last.
1
3
A7:A0 specifies the FIFO address.
Refer to READ Timing (1) for Address Setup Time and Address Hold Time.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
4. It is possible to increase t by setting the DMA interval register (DMAINTVL).
2
A7:A0
DREQ
t2
t1
CS
t5
t3
RD
t4
DOUT
DATA OUT
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