PEDL60851C-02
ML60851C
¡ Semiconductor
DMA Transfer Timing (6)
Memory to ML60851C (Single Transfer, Dual Address Mode)
Parameter
DREQ Disable Time
DREQ Enable Time
FIFO Access Time
Symbol
Condition
Min.
—
Max.
20
Unit
ns
Note
t1
t2
t3
t4
t5
Load 20 pF
—
63
ns
4
1
FIFO WRITE
42
—
ns
Write Data Setup Time
Write Data Hold Time
30
—
ns
2
—
ns
8-bit DMA
63
—
ns
2
3
Recovery Time
t6
16-bit DMA
105
—
ns
Notes: 1. When in Dual Address mode, the DACK is ignored.
t and t are defined depending on CS or WR which becomes active last.
1
3
Refer to WRITE Timing (1) for Address Setup Time and Address Hold Time.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
4. It is possible to increase t by setting the DMA interval register (DMAINTVL).
2
A7:A0
DREQ
t1
t2
CS
t6
t3
WR
t5
t4
DIN
57/67
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