PEDL60851C-02
ML60851C
¡ Semiconductor
TIMING DIAGRAM
READ Timing (1)
(Address Separate, ADSEL = 0)
Parameter
Address Setup Time (RD)
Address Setup Time (CS)
Address (CS) Hold Time
Read Data Delay Time
Read Data Hold Time
Recovery Time
Symbol
1 (RD)
Condition
Min.
21
10
0
Max.
—
Unit
ns
Note
t
5
5
2
1
t1 (CS)
—
ns
t2
t3
t4
t5
t6
—
ns
Load 20 pF
Load 20 pF
FIFO READ
FIFO READ
—
0
25
ns
25
ns
63
42
—
ns
3
4
FIFO Access Time
—
ns
Notes: 1. t3 is defined depending upon CS or RD which becomes active last.
2. t2 is defined depending upon CS or RD which becomes active first.
3. 3-clocktimeofoscillationclock(clockperiod: 21ns). ItisrequiredforincrementofFIFO.
4. 2-clocktimeofoscillationclock(clockperiod: 21ns). ItisrequiredforincrementofFIFO.
5. t1 is required for reading FIFO. t1 is defined when either t1(CS) or t1(RD) is satisfied.
A7:A0
t1
t2
t6
CS
RD
t5
t3
t4
AD7:AD0
DATA OUT
48/67
OKI [ OKI ELECTRONIC COMPONETS ]
