––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ ML53612 ■
5.6 Stream Switch Routing Registers, AR = 1007h:1000h (Ch. 7:0)
Note: To ensure compatibility with possible future versions of this device, write “0” to all "Reserved" bits in the
routing registers. All "Reserved" routing registers read-back "0".
DR_0
[4:0]
Definition
Input Data Stream [4:0]
Reserved (write zero)
[7:5]
Input Data Stream [4:0] (Read/Write)
00h
01h
02h
•
→
→
→
CT_D_[0] (Default)
CT_D_[1]
CT_D_[2]
•
•
•
1eh
1fh
→
→
CT_D_[30]
CT_D_[31]
DR_1
Definition
[4:0]
[6:5]
7
Output Data Stream [4:0]
Reserved (write zero)
Output Enable
Output Data Stream [4:0] (Read/Write)
00h
01h
02h
•
→
→
→
CT_D_[0] (Default)
CT_D_[1]
CT_D_[2]
•
•
•
1eh
1fh
→
→
CT_D_[30]
CT_D_[31]
Output Enable (Read/Write)
0
1
→
→
Output Disabled (Default)
Output Enabled
DR_2
[1:0]
[7:2]
Definition
Partition [1:0]
Reserved (write zero)
Partition [1:0] (Read/Write)
Selects which time-slots are used when rate conversion is taking place. See the following table for a
description of the partition function.
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