FEDL2250DIGEST-01
OKI Semiconductor
ML2252/54-XXX, ML22Q54
To read the channel status, input “L” level to CS and RD pins. DQ pin will output the channel status in
synchronization with SCK clock.
The selection of rising/falling edge of SCK clock, similar to when inputting the commands and data, is determined
by the level at SCK pin at the falling edge of CS pin.
The status signals in the parallel interface are output to D7 to D0 pins sequentially from D7.
Status Read Timing
• SCK Rising Edge Operation
CS (I)
RD (I)
SCK (I)
Hi-Z
Hi-Z
DO (O)
D7 D6 D5 D4 D3 D2 D1 D0
• SCK Falling Edge Operation
CS (I)
RD (I)
SCK (I)
Hi-Z
Hi-Z
DO (O)
D7 D6 D5 D4 D3 D2 D1 D0
20/31
OKI [ OKI ELECTRONIC COMPONETS ]
