¡ Semiconductor
MD56V62160/H
Bank Interleave Page Read Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
*Note1
RAS
CAS
RAa
CAa
RCb
CCb
CAc
CCd
CAe
ADDR
A13
A12
A10
DQ
RAa
RCa
QAa0 QAa1 QAa2 QAa3 QCb0 QCb1 QCb2 QCb3 QAc0 QAc1 QCd0 QCd1 QAe0 QAe1
lROH
WE
UDQM,
LDQM
Row Active
(A-Bank)
Row Active
(C-Bank)
Read Command
(C-Bank)
Precharge Command
(A-Bank)
Read Command
(A-Bank)
Read Command
(C-Bank)
Read Command
(A-Bank)
Read Command
(A-Bank)
*Note:
1. CS is ignored when RAS, CAS and WE are high at the same cycle.
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