¡ Semiconductor
MD56V62160/H
Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
*Note1
*Note1
CKE
CS
RAS
CAS
Ra
Ca
Cb
Cc
ADDR
A13
A12
Ra
A10
Qa0 Qa1
Qa2
Qa2
Qb0 Qb1
Qb0 Qb1
Dc0
Dc2
DQ1 - 8
tOHZ
tOHZ
*Note3
*Note4
DQ9 - 16
Qa0
Qa3
Dc0 Dc1
*Note2
WE
LDQM
*Note4
UDQM
Row Active
Read
DQM
CLOCK
Suspension
Read
Command
Write
DQM
Write
DQM
Read DQM
Read
Write
CLOCK
Read DQM
Command
Command Suspension
*Notes: 1. When Clock Suspension is asserted, the next clock cycle is ignored.
2. When LDQM and UDQM are asserted, the read data after two clock cycles is masked.
3. When LDQM and UDQM are asserted, the write data in the same clock cycle is masked.
4. When LDQM is set High, the input/output data of DQ1 - DQ8 is masked.
When UDQM is set High, the input/output data of DQ9 - DQ16 is masked.
21/28
OKI [ OKI ELECTRONIC COMPONETS ]
