¡ Semiconductor
MD56V62160/H
Page Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4
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CLK
High
CKE
CS
Bank A Active
RAS
CAS
lCCD
Ca0
Cb0
Cc0
Cd0
ADDR
A13
A12
A10
DQ
Qa0 Qa1 Qb0 Qb1
Dc0 Dc1 Dd0
*Note2
tWR
lOWD
WE
*Note1
UDQM,
LDQM
Read Command Read Command
Write Command Write Command
Precharge Command
*Notes: 1. To write data before a burst read ends, UDQM and LDQM should be asserted three cycles prior to the
write command to avoid bus contention.
2. To assert row precharge before a burst write ends, wait tWR after the last write data input.
Input data during the precharge input cycle will be masked internally.
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