¡ Semiconductor
MD56V62160/H
*Notes: 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE, UDQM, and
LDQM are invalid.
2. When issuing an active, read or write command, the bank is selected by A12 and A13.
A12
0
A13
0
Active, read or write
Bank A
0
1
Bank B
1
0
Bank C
1
1
Bank D
3. The auto precharge function is enabled or disabled by the A10 input when the read or write command
is issued.
A10
0
A12
0
A13
0
Operation
After the end of burst, bank A holds the idle status.
After the end of burst, bank A is precharged automatically.
After the end of burst, bank B holds the idle status.
After the end of burst, bank B is precharged automatically.
After the end of burst, bank C holds the idle status.
After the end of burst, bank C is precharged automatically.
After the end of burst, bank D holds the idle status.
After the end of burst, bank D is precharged automatically.
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
4. When issuing a precharge command, the bank to be precharged is selected by the A10, A12 and A13
inputs.
A10
0
A12
0
A13
0
Operation
Bank A is precharged.
Bank B is precharged.
Bank C is precharged.
Bank D is precharged.
All banks are precharged.
0
0
1
0
1
0
0
1
1
1
X
X
5. The input data and the write command are latched by the same clock (Write latency = 0).
6. The output is forced to high impedance by (1 CLK + tOHZ) after UDQM, LDQM entry.
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