TDA6650TT; TDA6651TT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
50 µs
ADDRESS
BYTE
ADDRESS
BYTE
DIVIDER DIVIDER CONTROL CONTROL CONTROL CONTROL
STOP
START
START
2
BYTE 1
BYTE 2
BYTE 1
BYTE 2
BYTE 1
BYTE 2
2
I C-bus transmission dedicated to
the MOPLL
I C-bus transmission
dedicated to
another IC
fce921
Fig 4. Example of I2C-bus transmission frame
Table 6.
Name
I2C-bus write data format
Byte
Bit
Ack
MSB[1]
LSB
Address byte
1
2
3
4
1
1
0
0
0
MA1
MA0
N9
R/W = 0 A
Divider byte 1 (DB1)
Divider byte 2 (DB2)
0
N14
N6
N13
N5
N12
N4
T1
0
N11
N3
N10
N2
N8
A
A
A
A
A
N7
1
N1
N0
Control byte 1 (CB1);
see Table 7
T/A = 1 T2
T0
R2
R1
R0
1
T/A = 0
CP1
0
ATC
BS4
AL2
BS3
AL1
BS2
AL0
BS1
Control byte 2 (CB2)
5
CP2
CP0
BS5
[1] MSB is transmitted first.
Table 7.
Description of write data format bits
Description
Bit
A
acknowledge
MA1 and MA0
R/W
programmable address bits; see Table 8
logic 0 for write mode
N14 to N0
programmable LO frequency;
N = N14 × 214 + N13 × 213 + N12 × 212 + ... + N1 × 21 + N0
T/A
test/AGC bit
T/A = 0: the next 6 bits sent are AGC settings
T/A = 1: the next 6 bits sent are test and reference divider ratio settings
test bits; see Table 9
T2, T1 and T0
R2, R1 and R0
ATC
reference divider ratio and programmable frequency step; see Table 10
AGC current setting and time constant; capacitor on pin AGC = 150 nF
ATC = 0: AGC current = 220 nA; AGC time constant = 2 s
ATC = 1: AGC current = 9 µA; AGC time constant = 50 ms
AGC take-over point bits; see Table 11
AL2, AL1 and AL0
CP2, CP1 and CP0 charge pump current; see Table 12
BS5, BS4, BS3, BS2 PMOS ports control bits
and BS1
BSn = 0: corresponding port is off, high-impedance state (status at
power-on reset)
BSn = 1: corresponding port is on; VO = VCC − VDS(sat)
TDA6650TT_6651TT_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 10 January 2007
9 of 54
NXP [ NXP ]
