TDA6650TT; TDA6651TT
NXP Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
the reference divider ratio, depending on the step frequency selected. The crystal
oscillator requires a 4 MHz crystal in series with an 18 pF capacitor between pins XTAL1
and XTAL2.
The output of the phase comparator drives the charge pump and the loop amplifier
section. This amplifier has an on-chip high voltage drive transistor. Pin CP is the output of
the charge pump, and pin VT is the pin to drive the tuning voltage to the varicap diodes of
the oscillators and the tracking filters. The loop filter has to be connected between pins CP
and VT. The spurious signals introduced by the fractional divider are automatically
compensated by the spurious compensation block.
It is possible to drive the clock input of a digital demodulation IC from pin XTOUT with the
4 MHz signal from the crystal oscillator. This output is also used to output 1⁄2fdiv and fcomp
signals in a specific test mode (see Table 9). It is possible to switch off this output, which is
recommended when it is not used.
For test and alignment purposes, it is also possible to release the tuning voltage output by
selecting the sinking mode (see Table 9), and by applying an external voltage on pin VT.
In addition to the BS1 and BS2 output ports that are used for the band selection, there are
three general purpose ports BS3, BS4 and BS5. All five ports are PMOS open-drain type,
each with 15 mA drive capability. The connection for port BS5 and the ADC input is
combined on one pin. It is not possible to use the ADC if port BS5 is used.
The AGC detector compares the level at the IF amplifier output to a reference level which
is selected from 6 different levels via the I2C-bus. The time constant of the AGC can be
selected via the I2C-bus to cope with normal operation as well as with search operation.
When the output level on pin AGC is higher than the threshold VRMH, then bit AGC = 1.
When the output level on pin AGC is lower than the threshold VRML, then bit AGC = 0.
Between these two thresholds, bit AGC is not defined. The status of the AGC bit can be
read via the I2C-bus according to the read mode as described in Table 15.
7.2 I2C-bus voltage
The I2C-bus lines SCL and SDA can be connected to an I2C-bus system tied to 2.5 V,
3.3 V or 5 V. The choice of the bus input threshold voltages is made with pin BVS that can
be left open-circuit, connected to the supply voltage or to ground (see Table 5).
Table 5.
I2C-bus voltage selection
Pin BVS connection
Bus voltage
Logic level
LOW
HIGH
To ground
Open-circuit
To VCC
2.5 V
3.3 V
5 V
0 V to 0.75 V
0 V to 1.0 V
0 V to 1.5 V
1.75 V to 5.5 V
2.3 V to 5.5 V
3.0 V to 5.5 V
7.3 Phase noise, I2C-bus traffic and crosstalk
While the TDA6650TT; TDA6651TT is dedicated for hybrid terrestrial applications, the low
noise PLL will clean up the noise spectrum of the VCOs close to the carrier to reach noise
levels at 1 kHz offset from the carrier compatible with e.g. DVB-T reception.
TDA6650TT_6651TT_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 10 January 2007
7 of 54
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