Philips Semiconductors
Product specification
Economy Autosync Deflection Controller
(EASDC)
TDA4858
PLL2 phase detector
Output stage for line drive pulses
The PLL2 phase detector is similar to the PLL1 detector
and compares the line flyback pulse at HFLB (pin 1) with
the oscillator sawtooth voltage. The PLL2 detector thus
compensates for the delay in the external horizontal
deflection circuit by adjusting the phase of the HDRV
(pin 7) output pulse.
An open-collector output stage allows direct drive of an
inverting driver transistor because of a low saturation
voltage of 0.3 V at 20 mA. To protect the line deflection
transistor, the output stage is disabled (floating) for low
supply voltage at VCC (see Fig.14).
The duty factor of line drive pulses is slightly dependent on
the actual line frequency. This ensures optimum drive
conditions over the whole frequency range.
The phase between horizontal flyback and horizontal sync
can be controlled at HPOS (pin 30).
If HPLL2 is pulled to ground, horizontal output pulses,
vertical output currents and B+ control driver pulses are
inhibited. This means, HDRV (pin 7), BDRV (pin 6)
VOUT1 (pin 13) and VOUT2 (pin 12) are floating in this
state. PLL2 and the frequency-locked loop are disabled,
and CLBL (pin 16) provides a continuous blanking signal.
X-ray protection
The X-ray protection input XRAY (pin 2) provides a voltage
detector with a precise threshold. If the input voltage at
XRAY exceeds this threshold for a certain time, an internal
latch switches the IC into protection mode. In this mode
several pins are forced into defined states:
This option can be used for soft start, protection and
power-down modes. When the HPLL2 voltage is released
again, an automatic soft start sequence will be performed
(see Fig.15).
Horizontal output stage (HDRV) is floating
B+ control driver stage (BDRV) is floating
Vertical output stages (VOUT1 and VOUT2) are floating
CLBL provides a continuous blanking signal
The soft start timing is determined by the filter capacitor at
HPLL2 (pin 31), which is charged with an constant current
during soft start. In the beginning the horizontal driver
stage generates very small output pulses. The width of
these pulses increases with the voltage at HPLL2 until the
final duty factor is reached. At this point BDRV (pin 6),
VOUT1 (pin 13) and VOUT2 (pin 12) are re-enabled.
The voltage at HPLL2 continues to rise until PLL2 enters
its normal operating range. The internal charge current is
now disabled. Finally PLL2 and the frequency-locked loop
are enabled, and the continuous blanking at CLBL is
removed.
The capacitor connected to HPLL2 (pin 31) is
discharged.
To reset the latch and return to normal operation, VCC has
to be temporarily switched off.
Vertical oscillator and amplitude control
This stage is designed for fast stabilization of vertical
amplitude after changes in sync frequency conditions.
The free-running frequency fosc(V) is determined by the
resistor RVREF connected to pin 23 and the capacitor
CVCAP connected to pin 24. The value of RVREF is not only
optimized for noise and linearity performance in the whole
vertical and EW section, but also influences several
internal references. Therefore the value of RVREF must not
be changed. Capacitor CVCAP should be used to select the
free-running frequency of the vertical oscillator in
accordance with the following formula:
Horizontal phase adjustment
HPOS (pin 30) provides a linear adjustment of the relative
phase between the horizontal sync and oscillator
sawtooth. Once adjusted, the relative phase remains
constant over the whole frequency range.
Application hint: HPOS is a current input, which provides
an internal reference voltage while IHPOS is in the specified
adjustment current range. By grounding HPOS the
symmetrical control range is forced to its centre value,
therefore the phase between horizontal sync and
horizontal drive pulse is only determined by PLL2.
1
fosc (V)
=
-----------------------------------------------------------
10.8 × RVREF × CVCAP
To achieve a stabilized amplitude the free-running
frequency fosc(V), without adjustment, should be at least
10% lower than the minimum trigger frequency.
The contributions shown in Table 2 can be assumed.
1997 Oct 27
8
NXP [ NXP ]
