Philips Semiconductors
Product specification
Economy Autosync Deflection Controller
(EASDC)
TDA4858
PLL2 soft start sequence
MBG553
l pagewidth
V
HPLL2
4.4 V continuous blanking off
PLL2 enabled
frequency detector enabled
3.7 V HDRV duty factor has reached nominal value
BDRV enabled
VOUT1 and VOUT2 enabled
0.5 V
HDRV duty factor begins to increase
time
a. PLL2 start-up sequence.
MBG552
agewidth
V
HPLL2
4.4 V continuous blanking CLBL (pin 16) activated
PLL2 disabled
frequency detector disabled
3.7 V HDRV duty factor begins to decrease
BDRV floating
VOUT1 and VOUT2 floating
0.5 V
HDRV floating
time
b. PLL2 shut-down sequence.
Fig.15 PLL2 soft start sequence.
30
1997 Oct 27
NXP [ NXP ]
