Philips Semiconductors
Product specification
Economy Autosync Deflection Controller
(EASDC)
TDA4858
Start-up and shut-down sequence
ook, full pagewidth
MBG555
V
CC
V
> 8.5 V
8.5 V continuous blanking off
CC
and
> 4.4 V
PLL2 enabled
frequency detector enabled
V
HPLL2
V
> 8.2 V
8.2 V video clamping pulse enabled
BDRV enabled
CC
and
V
> 3.7 V
VOUT1 and VOUT2 enabled
HPLL2
(1)
5.8 V
PLL2 soft start sequence begins
4.0 V
continuous blanking CLBL (pin 16) activated
time
(1) See Fig 15 for PLL2 soft start.
a. Start-up sequence.
MBG554
agewidth
V
CC
8.5 V continuous blanking CLBL (pin 16) activated
PLL2 disabled
frequency detector disabled
8.0 V video clamping pulse disabled
BDRV floating
VOUT1 and VOUT2 floating
5.6 V
HDRV floating
4.0 V continuous blanking disappears
time
b. Shut-down sequence.
Fig.14 Start-up sequence and shut-down sequence.
29
1997 Oct 27
NXP [ NXP ]
