Philips Semiconductors
Product specification
Economy Autosync Deflection Controller
(EASDC)
TDA4858
composite sync (TTL)
handbook, full pagewidth
at HSYNC (pin 15)
internal integration of
composite sync
internal vertical
trigger pulse
PLL1 control voltage
at HPLL1 (pin 26)
clamping and blanking
pulses at CLBL (pin 16)
(triggered on leading edge)
clamping and blanking
pulses at CLBL (pin 16)
(triggered on trailing edge)
MGD098
a. Reduced influence of vertical sync on horizontal phase.
handbook, full pagewidth
composite sync (TTL)
at HSYNC (pin 15)
clamping and blanking
pulses at CLBL (pin 16)
(triggered on leading edge)
clamping and blanking
pulses at CLBL (pin 16)
(triggered on trailing edge)
MGD099
b. Generation of video clamping pulses during vertical sync with serration pulses.
Fig.11 Pulse diagrams for composite sync applications.
1997 Oct 27
26
NXP [ NXP ]
