Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOS
TM
transistor
PHN210T
1E-01
Sub-Threshold Conduction
10
9
Source-Drain Diode Current, IF (A)
VGS = 0 V
1E-02
min
typ
max
8
7
6
5
4
Tj = 25 C
3
2
1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
1E-03
150 C
1E-04
1E-05
1E-06
0
1
2
3
4
5
Drain-Source Voltage, VSDS (V)
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Non-repetitive Avalanche current, IAS (A)
10
PHN210
Capacitances, Ciss, Coss, Crss (pF)
1000
25 C
Ciss
1
100
Coss
Crss
VDS
tp
ID
Tj prior to avalanche =125 C
10
0.1
1
10
Drain-Source Voltage, VDS (V)
100
0.1
1E-06
1E-05
1E-04
Avalanche time, tp (s)
1E-03
1E-02
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.15. Maximum permissible non-repetitive
avalanche current (I
AS
) versus avalanche time (t
p
);
unclamped inductive load
Gate-source voltage, VGS (V)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
ID = 2.3A
Tj = 25 C
VDD = 15 V
1
2
3
4
5
6
7
Gate charge, QG (nC)
8
9
10
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
March 1999
5
Rev 1.000
PHILIPS [ NXP SEMICONDUCTORS ]
